In-Memory Half Adder Computation using CNTFET Transistors in 8T SRAM

Abstract

In modern applications as the transistor size is scaled down for high density chips, there are various limitations in CMOS such as mobility degradation, high leakage current, and higher standby power consumption. So, to overcome limitations imposed by CMOS, CNTFET is emerging as alternative option. The von-Neumann architecture is used in mostly all computing systems. In von-Neumann architecture, we must fetch data from memory to computer for computations and resend it to computer memory for further processing or storing. This causes large amount of energy consumption and delay in processing. To overcome the von-Neumann bottleneck, in-memory computation is being used nowadays. In the present work, first an in-memory computation circuit using virtual source carbon nanotube field-effect transistors (VS-CNTFET) in 8T SRAM is designed for improved performance. Next, a half adder circuit is also implemented and analyzed at different gate length of optimized VS-CNTFET using in-memory computation of NOR/NAND logics.