A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions

P. Le Du; Zhaohui Cai

doi:10.1007/978-981-97-0834-5_25

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A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions

P. Le Du Zhaohui Cai

Year: 2024 Lecture notes in computer science Pages: 439-454 Publisher: Springer Science+Business Media

DOI: 10.1007/978-981-97-0834-5_25

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Keywords:

Computer science Reduced instruction set computing Instruction set Asynchronous communication Data compression Pipeline (software) Lossless compression Computer hardware Embedded system Computer architecture Operating system Algorithm

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Algorithms and Data Compression

Physical Sciences → Computer Science → Artificial Intelligence

Time Series Analysis and Forecasting

Physical Sciences → Computer Science → Signal Processing

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions

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