A RISC-V Processor with Custom Instructions for Spiking Neural Network Acceleration

Feihong Dong; Lin-Jie Jiang; Cunyang Luan; Rong Sun; Yongkui Yang

doi:10.1109/icta64028.2024.10860426

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A RISC-V Processor with Custom Instructions for Spiking Neural Network Acceleration

Feihong Dong Lin-Jie Jiang Cunyang Luan Rong Sun Yongkui Yang

Year: 2024 Pages: 222-223

DOI: 10.1109/icta64028.2024.10860426

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Keywords:

Computer science Acceleration Reduced instruction set computing Spiking neural network Coprocessor Hardware acceleration Artificial neural network Parallel computing Computer architecture Embedded system Instruction set Computer hardware Field-programmable gate array Artificial intelligence

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Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Neuroscience and Neural Engineering

Life Sciences → Neuroscience → Cellular and Molecular Neuroscience

CCD and CMOS Imaging Sensors

Physical Sciences → Engineering → Electrical and Electronic Engineering

A RISC-V Processor with Custom Instructions for Spiking Neural Network Acceleration

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