Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]

Abstract

Abstract: A wide range of present and future applications strive to develop highly efficient central processing units (CPUs). One particular design that meets these requirements is the RISC V processor micro-architecture. The RISC-V Instruction Set Architecture (ISA) provides the necessary support for this micro-architecture. The instruction set architecture and microarchitecture are crucial components in processor design. Among these components, the multiplier and divider circuits exhibit a relatively high level of hardware complexity compared to other stages of instruction execution. Therefore, it is essential to consider these factors when designing the core micro-architecture. The size, power, and performance of a core are determined by the construction of an appropriate hardware circuit capable of handling multiplication and division operations. The core consists of four phases, with each instruction being executed within these stages, except for data storage and retrieval. Arithmetic operations can be completed within a single clock cycle. However, division and multiplication operations are repeated in order to reduce the latency of the critical path.