A Power-Efficient Core Micro-Architecture Based on RISC-V Instruction Set Architecture

Chatrapathi Srs Krishna P; E. Prabhu

doi:10.1109/tensymp61132.2024.10752175

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A Power-Efficient Core Micro-Architecture Based on RISC-V Instruction Set Architecture

Chatrapathi Srs Krishna P E. Prabhu

Year: 2024 Pages: 1-6

DOI: 10.1109/tensymp61132.2024.10752175

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Keywords:

Computer architecture Computer science Architecture Instruction set Set (abstract data type) Reduced instruction set computing Core (optical fiber) Microarchitecture Many core Embedded system Parallel computing Programming language Telecommunications

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Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

A Power-Efficient Core Micro-Architecture Based on RISC-V Instruction Set Architecture

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Citation History

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