Research and design of low-power, high-performance processor based on RISC-V instruction set architecture

Abstract

Abstract In embedded IoT applications, in order to meet the needs of small area, low power consumption, and high performance, this paper designs a 32-bit low-power, high-performance microprocessor based on the RISC-V instruction set architecture. It uses a 3-stage pipeline structure with static branch prediction function, supports RV32IM instruction set, and adopts AHB bus as the control bus. The logic function of the processor was verified under the iverilog environment, and the simulation results showed that the processor can run normally. The CoreMark score of 2.38 CoreMark/MHz was measured by running the CoreMark running program, and it supports FreeRTOS transplantation. The analysis and verification results show that the design can be well applied to small-area, low-power embedded application scenarios.