AI Edge Processor Using RISC - V Instruction Set Architecture Design

Shilpa Anil Borade; Saurabh Bansod; Anirban Jyoti Hati; Shashank Kumar Singh

doi:10.1109/ginotech63460.2025.11076631

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AI Edge Processor Using RISC - V Instruction Set Architecture Design

Shilpa Anil Borade Saurabh Bansod Anirban Jyoti Hati Shashank Kumar Singh

Year: 2025 Pages: 1-8

DOI: 10.1109/ginotech63460.2025.11076631

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Keywords:

Reduced instruction set computing Computer architecture Instruction set Computer science Architecture Enhanced Data Rates for GSM Evolution Microarchitecture Set (abstract data type) Parallel computing Embedded system Programming language Artificial intelligence

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CCD and CMOS Imaging Sensors

Physical Sciences → Engineering → Electrical and Electronic Engineering

Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

AI Edge Processor Using RISC - V Instruction Set Architecture Design

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