Architecture design of a RISC-processor for prolog

Peter Deussen; Wolfgang Rosenstiel; Klaus Erik Schaufer; Jörg Wedeck

doi:10.1016/0165-6074(89)90028-8

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Architecture design of a RISC-processor for prolog

Peter Deussen Wolfgang Rosenstiel Klaus Erik Schaufer Jörg Wedeck

Year: 1989 Journal: Microprocessing and Microprogramming Vol: 27 (1-5)Pages: 101-108 Publisher: Elsevier BV

DOI: 10.1016/0165-6074(89)90028-8

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Keywords:

Prolog Computer science Reduced instruction set computing Programming language Cache Instruction set Architecture Computer architecture Parallel computing Set (abstract data type) Microarchitecture

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Logic, programming, and type systems

Physical Sciences → Computer Science → Artificial Intelligence

Formal Methods in Verification

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Architecture design of a RISC-processor for prolog

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