Wafer scale interconnections for GaAs packaging — applications to RISC architecture

doi:10.1016/0141-9331(87)90487-x

JOURNAL ARTICLE

Wafer scale interconnections for GaAs packaging — applications to RISC architecture

Year: 1987 Journal: Microprocessors and Microsystems Vol: 11 (6)Pages: 339-339 Publisher: Elsevier BV

DOI: 10.1016/0141-9331(87)90487-x

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Keywords:

Computer science Wafer Wafer-scale integration Embedded system Chip-scale package Architecture Scale (ratio) Computer architecture Computer hardware Very-large-scale integration Telecommunications Materials science Optoelectronics Chip

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3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Semiconductor Lasers and Optical Devices

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Wafer scale interconnections for GaAs packaging — applications to RISC architecture

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