CMOS compatible SOI nanowire FET with charged dielectric for temperature sensing applications

Abstract

Abstract This paper reports a novel concept of a low voltage low power temperature sensor with a 300–370 K operating temperature range, based on a silicon-on-insulator (SOI) nanowire FET with standard SOI CMOS technology. The novel design combines a top-down silicon nanowire and an electrostatically formed nanowire, capacitively coupled to a back-gate electrode. A surface charged silicon nitride layer is used to deplete the upper part of the nanowire, while a back-gate controls the size and location of the electrostatically formed nanowire. The device operates in a regime similar to the subthreshold regime of a nanowire transistor and features a very high temperature response, expressed by the temperature coefficient of current (TCC = 6 % K −1 at 0.4 < I DS < 5 pA for a single nanowire). The device can be easily integrated into a nanowire-based sensor array.