FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

Im. Lavanya; A. M. Guna Sekhar

JOURNAL ARTICLE

FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

Year: 2018 Journal: International Journal of Scientific Research in Science and Technology Vol: 4 (2)Pages: 219-225 Publisher: Technoscience Academy

Get Full-Text PDF Get Analytical Report

Keywords:

Field-programmable gate array Gas compressor Multiplier (economics) Single-precision floating-point format Computer science Floating point Computer hardware Embedded system Algorithm Engineering

Metrics

Cited By

0.50

FWCI (Field Weighted Citation Impact)

Refs

0.66

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

Numerical Methods and Algorithms

Physical Sciences → Computer Science → Computational Theory and Mathematics

Digital Filter Design and Implementation

Physical Sciences → Computer Science → Signal Processing

Embedded Systems and FPGA Design

Physical Sciences → Engineering → Control and Systems Engineering

FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors

Metrics

Citation History

Topics

Related Documents

High-Speed Single Precision Floating Point Multiplier using CORDIC Algorithm

FPGA implementation of delay optimized single precision floating point multiplier

FPGA implementation of single precision inexact floating-point multiplier using Vedic algorithm

FPGA Implementation of Double Precision Floating Point Multiplier

FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog