BOOK-CHAPTER
FPGA implementation of single precision inexact floating-point multiplier using Vedic algorithm
Keywords:
Field-programmable gate array Multiplier (economics) Computer science Floating point Single-precision floating-point format Algorithm Double-precision floating-point format Arithmetic Parallel computing Computer hardware Mathematics
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Citation History
Topics
Numerical Methods and Algorithms
Physical Sciences → Computer Science → Computational Theory and Mathematics
Analog and Mixed-Signal Circuit Design
Physical Sciences → Engineering → Biomedical Engineering
Evolutionary Algorithms and Applications
Physical Sciences → Computer Science → Artificial Intelligence
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