BOOK-CHAPTER

FPGA Implementation of Single-Precision Floating Point Multiplication with Karatsuba Algorithm Using Vedic Mathematics

K V GowreesrinivasP. Samundiswary

Year: 2017 Smart innovation, systems and technologies Pages: 515-524   Publisher: Springer Nature
Keywords:
Adder Verilog Multiplier (economics) Arithmetic Single-precision floating-point format Multiplication (music) Subtraction Floating point Field-programmable gate array Computer science Multiplication algorithm IEEE floating point Carry-save adder Digital signal processing Carry (investment) Algorithm Computer hardware Mathematics Binary number

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Citation History

Topics

Numerical Methods and Algorithms
Physical Sciences →  Computer Science →  Computational Theory and Mathematics
Low-power high-performance VLSI design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Digital Filter Design and Implementation
Physical Sciences →  Computer Science →  Signal Processing
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