JOURNAL ARTICLE

Delay Defect Diagnosis Methodology Using Path Delay Measurements

Eun Jung JangJaeyong ChungJacob A. Abraham

Year: 2015 Journal:   IEICE Transactions on Electronics Vol: E98.C (10)Pages: 991-994   Publisher: Institute of Electronics, Information and Communication Engineers

Abstract

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.

Keywords:
Delay calculation Path (computing) Algorithm Computer science Process (computing) Scaling Real-time computing Reliability engineering Propagation delay Mathematics Engineering

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Topics

VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture
Integrated Circuits and Semiconductor Failure Analysis
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
VLSI and FPGA Design Techniques
Physical Sciences →  Engineering →  Electrical and Electronic Engineering

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