JOURNAL ARTICLE

An implicit path-delay fault diagnosis methodology

Sanjeevikumar PadmanabanSpyros Tragoudas

Year: 2003 Journal:   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol: 22 (10)Pages: 1399-1408   Publisher: Institute of Electrical and Electronics Engineers

Abstract

The first nonenumerative framework for diagnosing path delay faults (PDFs) using zero suppressed binary decision diagrams is introduced. We show that fault-free PDFs with certain validated nonrobust test may be used together with fault-free robustly tested faults to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero-suppressed binary decision diagram. The proposed method is space and time nonenumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS'85 benchmarks show that the proposed technique is on average three times more efficient than the existing techniques.

Keywords:
Binary decision diagram Fault (geology) Path (computing) Computer science Algorithm Set (abstract data type) Binary number Zero (linguistics) Diagram Mathematics Arithmetic

Metrics

28
Cited By
1.68
FWCI (Field Weighted Citation Impact)
17
Refs
0.84
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture
Radiation Effects in Electronics
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Software Testing and Debugging Techniques
Physical Sciences →  Computer Science →  Software

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