A low-voltage latch-adder based tree multiplier

Abstract

For achieving low power and high performance simultaneously, we propose a new low-voltage latch-adder based Wallace-tree multiplier. By choosing the best circuit-structure of the latch-adder for low voltage, while optimizing the number and positions of latch-adders, the proposed 0.18-μm 0.9V 32×32 2's complement multiplier can operate above 60MHz. As compared to the tree multiplier implementing the traditional latch-adder technique, the new tree multiplier with all the proposed techniques achieves a 22.3∼23.7% delay improvement with a 5.5∼3.3% power reduction. All best latch-adder based tree multipliers have a smaller power-delay-product than the tree multipliers without using the latch-adder technique.