Low power wallace tree multiplier using modified full adder

Abstract

Achieving high speed integrated circuits with low power consumption is a major concern for the VLSI circuit designers. Most arithmetic operations are done using multiplier, which is the major power consuming element in the digital circuits. Basically the process of multiplication is realized in hardware in terms of shift and add operation. The optimization of adder has led to the improvement in performance of multiplier. In this paper, a modified full adder using multiplexer is proposed to achieve low power consumption of multiplier. To analyze the efficiency of proposed design, the conventional Wallace tree multiplier structure is used. The designs are developed using Verilog HDL and the functionalities are verified through simulation using Quartus II. The designs are synthesized in Synopsys Design Compiler using SAED90nm CMOS technology. The ASIC synthesis results of the proposed multiplier shows an average reduction of 37.45% in power consumption, 45.75% in area, and 17.65% in delay compared to the existing approaches.