Design of low power Wallace tree multiplier using modified full adder

Abstract

High speed and energy-efficient of a device are essential in the electronics industry due to the high demand for multimedia usage and fast technology. Multipliers play a vital role, especially in the processor's integrated circuits, microprocessors, filters, and arithmetic units. Wallace tree multiplier works in parallel, making it an efficient multiplier in terms of area and speed. Internally, a multiplier consists of Adder, which is full Adder (FA) and half Adder (HA). Full adders give a significant contribution to making a multiplier that works very well. A processor or chip performs very efficiently and effectively when running at high speed, in a small area, and at low power. Modification of full Adder in Wallace tree multiplier helps to consume low power during multiplication. In this project, 4-bit and 8-bit Wallace tree multipliers are designed. The design is developed in Verilog HDL and simulated the functionalities using Quartus II software. Mentor Graphic software was used to produce the final layout of 8 x 8-bit Wallace tree multiplier. The modified Wallace tree multiplier shows 64.97mW power lower than the conventional multiplier, which was 65.88mW.