Monolithic CMOS Front-end Electronics With Analog Pipelining

Abstract

Basic functional blocks have been designed and tested: Bipoltest, CSI, SAPE and PPAD which are a front-end amplifier, a current sampling integrator, an analog pipeline and an analog/digital converter respectively. These functional blocks will eventually be combined in a single chip, and this processor will be the starting point for the HARP architecture. The signal amplifier peaking time for low capacitance detector elements is less than 15 ns. The sampling rate of the pipeline element in the 3 pn CMOS is measured to be 20 MHz with a dynamic range of k1.2 pC of input charge which corresponds to 11 bits and the sampling rate in the 1.5 pn technology is over 60 MHz. The ADC operates at 1 MHz sampling rate with 12 mW for 11 bits precision.