primary outputs to primary inputs. The proposed method is an alternative to fault simulation. It requires no delay size based fault modeh and considers only the fault-free circuit. consquently, this approach is faster, reliable and requires less memory than conventional fault simulation. The class offaultsknown as delayfauh investigatedin this paper. The Diagnosis process is autOdicallY implemented ajter the detection Of a fault in a circuit. Unfortunately, the existing methodologies for locating timing failures on digital circuits have shown certain deficiencies. A new and reliable method for &lay faulr 2, Detection of a Delay Fault diagnosis, based on the symbolic simulation of the fault-f?ee circuit, is presented.
Patrick GirardC. LandraultS. Pravossoudovitch
Min JinRen LiZengbing XuXudong Zhao
Zhiyuan WangMalgorzata Marek-SadowskaKun-Han TsaiJanusz Rajski