Abstract

primary outputs to primary inputs. The proposed method is an alternative to fault simulation. It requires no delay size based fault modeh and considers only the fault-free circuit. consquently, this approach is faster, reliable and requires less memory than conventional fault simulation. The class offaultsknown as delayfauh investigatedin this paper. The Diagnosis process is autOdicallY implemented ajter the detection Of a fault in a circuit. Unfortunately, the existing methodologies for locating timing failures on digital circuits have shown certain deficiencies. A new and reliable method for &lay faulr 2, Detection of a Delay Fault diagnosis, based on the symbolic simulation of the fault-f?ee circuit, is presented.

Keywords:
Fault (geology) Stuck-at fault Computer science Fault coverage Fault indicator Fault model Fault detection and isolation Digital electronics Process (computing) Electronic circuit Reliability engineering Real-time computing Engineering Electrical engineering Artificial intelligence

Metrics

7
Cited By
0.50
FWCI (Field Weighted Citation Impact)
19
Refs
0.67
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Topics

VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture
Integrated Circuits and Semiconductor Failure Analysis
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Radiation Effects in Electronics
Physical Sciences →  Engineering →  Electrical and Electronic Engineering

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