Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

P. Thangavel; V. P. Muthuswamy

doi:10.1016/0020-0190(93)90203-l

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Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

P. Thangavel V. P. Muthuswamy

Year: 1993 Journal: Information Processing Letters Vol: 46 (2)Pages: 89-94 Publisher: Elsevier BV

DOI: 10.1016/0020-0190(93)90203-l

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Keywords:

Computer science Parallel computing Matrix multiplication Scalability Multiplication (music) Operand Parallel algorithm Computation Algorithm Inefficiency Cost efficiency Analysis of parallel algorithms Mathematics

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Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

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