Cost‐effective algorithms for processor arrays with reconfigurable bus systems

Abstract

Abstract A processor array with a reconfigurable bus system (abbreviated to PARBS) is a computation model which consists of a processor array and a reconfigurable bus system. It is a very powerful computation model in that it possesses the ability to solve many problems efficiently. However, most existing efficient algorithms on PARBS's use a large number of processors to solve problems. For example, to determine the maximum (minimum) of n data items in O(l) time, O(n 2) processors are required [12]. To solve the all‐pairs shortest paths and the minimum spanning tree problems in O(log n) time, O(n 4) processors are required [20]. These networks will therefore become very expensive for large n. In this paper, we introduce the concept of iterative‐PARBS, which is similar to the FOR‐loop construct in sequential programming languages. The iterative‐PARBS is a building block through which the processing data can be routed several times. We can think of it as a “hardware subroutine.’’ Based on this scheme, it is possible to explore more cost‐effective, time‐efficient parallel algorithms for use in a PARBS. The following new results are derived in this study: 1. The minimum (maximum) of n data items can be determined in O(l) time on a PARBS with O(n 1+ϵ ) processors for any fixed 8 > 0.2. The all‐pairs shortest paths and the minimum spanning tree problems can be solved in O (log n) time on a PARBS with O(n 3+ϵ ) processors for any fixed 8 > 0.