Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

Sven-Ole Voigt; Malte Baesler; Stephanie Teufel

doi:10.1016/j.sysarc.2010.07.010

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Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

Sven-Ole Voigt Malte Baesler Stephanie Teufel

Year: 2010 Journal: Journal of Systems Architecture Vol: 56 (11)Pages: 561-576 Publisher: Elsevier BV

DOI: 10.1016/j.sysarc.2010.07.010

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Keywords:

Computer science Dataflow Control reconfiguration Scalability Field-programmable gate array Dataflow architecture Computer architecture Digital signal processing Architecture Parallel computing Embedded system Computer hardware Operating system

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

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