A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing

Akihiko Tsukahara; Akinori Kanasugi

doi:10.1007/s10015-014-0162-0

ScienceGate Book Chapters

JOURNAL ARTICLE

A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing

Akihiko Tsukahara Akinori Kanasugi

Year: 2014 Journal: Artificial Life and Robotics Vol: 19 (3)Pages: 233-238 Publisher: Springer Science+Business Media

DOI: 10.1007/s10015-014-0162-0

Get Full-Text PDF Get Analytical Report

Keywords:

Control reconfiguration Computer science Adder Field-programmable gate array Verilog Reduction (mathematics) Computer hardware Mode (computer interface) SIGNAL (programming language) Embedded system Mathematics

Metrics

Cited By

0.00

FWCI (Field Weighted Citation Impact)

Refs

0.09

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Topics

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing

Metrics

Topics

Related Documents

Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

Dynamically Reconfigurable Architectures for Digital Signal Processing Applications

Dynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing Architectures

APPLICATION OF DYNAMICALLY RECONFIGURABLE PROCESSORS IN DIGITAL SIGNAL PROCESSING

Dynamically Reconfigurable Dataflow Architecture for High-Performance Digital Signal Processing on Multi-FPGA Platforms