Reconfigurable digital architecture for high speed digital signal processing

Abstract

Low cost microprocessors and DSPs are optimized to perform arithmetic and logic operations on data having a xed size, typically 16,32 or 64 bit. On the other hand, their e ciency decreases when data shorter respect than their native wordlength are processed (more clock cycles per operation are required). Recently di erent solutions have been proposed to overcome this problem. Among those, the ones based on a main processor with a Recon gurable Unit used as hardware accelerator \nare the most interesting in terms of performance and exibility. Typically those architectures are similar to very small FPGA; they consist in arrays of Look-Up Tables (LUTs) interconnected by pass transistors networks. This work proposes a new Recon gurable Accelerator called ADAPTO Adderbased Dynamic Architecture for Processing Tailored Operators). The main different between ADAPTO and the others Recon gurable Units proposed in literature is the reduced hardware complexity in terms of silicon area. This feature give the possibility to integrate ADAPTO in embedded low cost microprocessors and DSPs (Digital Signal Processors), in fact, for these kind of processors, the area occupation and therefore the cost is a very critical aspect. The ADAPTO Unit supports both hardware recon guration and instruction execution in the same processor clock cycle. \nThese goals have been obtained with the multicontext approach using a recon gurable unit based on full adders, instead LUTs. As discussed in this work this choice allows to the multicontext technique a reduced wasting of hardware resources.