High-performance VLSI architecture for adaptive scaling

Philip P. Dang

doi:10.1117/12.651456

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High-performance VLSI architecture for adaptive scaling

Philip P. Dang

Year: 2006 Journal: Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE Vol: 6063 Pages: 60630C-60630C Publisher: SPIE

DOI: 10.1117/12.651456

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Abstract

This paper introduces an adaptive approach for image scaling. In addition, we present an efficient VLSI architecture to implement the proposed algorithm in hardware. The proposed architecture is designed to address the real-time constrain for high performance consumer products. A case study for printer application is presented.

Keywords:

Very-large-scale integration Computer science Architecture Computer architecture Scaling Embedded system Parallel computing Computer hardware Computer engineering

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Topics

Image and Signal Denoising Methods

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Medical Image Segmentation Techniques

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Advanced Vision and Imaging

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

High-performance VLSI architecture for adaptive scaling

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