VLSI architecture and design for high performance adaptive video scaling

Arun Raghupathy; Po‐Hsiang Hsu; K. J. Ray Liu; Nitin Chandrachoodan

doi:10.1109/iscas.1999.780028

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JOURNAL ARTICLE

VLSI architecture and design for high performance adaptive video scaling

Arun Raghupathy Po‐Hsiang Hsu K. J. Ray Liu Nitin Chandrachoodan

Year: 1999 Pages: 406-409 vol.4

DOI: 10.1109/iscas.1999.780028

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Abstract

In this paper, we develop an efficient architecture for video scaling based on the adaptive image scaling algorithm. We then develop the design of the computation units and perform synthesis to show that the chip area required to perform scaling from QCIF to 4CIF is about 20 mm/sup 2/ using 0.5 /spl mu/m technology.

Keywords:

Computer science Very-large-scale integration Scaling Computer architecture Computation Chip Architecture Integrated circuit design System on a chip Parallel computing Embedded system Computer hardware Algorithm Telecommunications

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Topics

Image and Signal Denoising Methods

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Advanced Image Processing Techniques

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

Advanced Data Compression Techniques

Physical Sciences → Computer Science → Computer Vision and Pattern Recognition

VLSI architecture and design for high performance adaptive video scaling

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