A high-throughput reconfigurable Viterbi decoder

Abstract

A reconfigurable Viterbi decoder with high throughput and low complexity is presented in this paper. The proposed Viterbi decoder supports constraint lengths ranging from 3-9, code rates in the range of 1/2-1/3, and arbitrary truncation lengths. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G. The proposed decoder is implemented on Xilinx XC5VLX330 device and the frequency achieved is 202 MHz with the throughput of 202 Mbps, which is apparently superior to the other current reconfigurable Viterbi decoders on the FPGA platform.