High performance reconfigurable Viterbi Decoder design for multi-standard receiver

Abstract

A Viterbi Decoder (VD) is employed to decode the convolutional codes, where convolutional codes are commonly used to encode digital data before transmission. However, there is a large variety of modern wireless communication standards; a flexible hardware platform that can be configured to support different standards is still needed. In this paper, a reconfigurable Viterbi decoder has been designed. The proposed Viterbi decoder has an architecture that supports constraint lengths 3, 5, and 7, and code rates 1/2 and 1/3 which makes it compatible with many common standards, like Wi-Max, WLAN, 3GPP2, GSM and LTE. The proposed Viterbi decoder has been simulated using Xilinx ISE 14.5 simulator and implemented with VHDL on Xilinx Zed board, Zynq-7000 FPGA using Xilinx iMPACT device configuration tool. Moreover, in the proposed architecture design, a modified add-compare-select unit that efficiently reduces power consumption by 26% and area by 21% is employed.