The design of a register renaming unit

B. Bishop; T.P. Kelliher; M.J. Irwin

doi:10.1109/glsv.1999.757371

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JOURNAL ARTICLE

The design of a register renaming unit

B. Bishop T.P. Kelliher M.J. Irwin

Year: 2003 Pages: 34-37

DOI: 10.1109/glsv.1999.757371

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Abstract

Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.

Keywords:

Register (sociolinguistics) Computer science Register file Register allocation Processor register Parallel computing Unit (ring theory) Shift register Computer architecture Arithmetic Programming language Computer hardware Instruction set Memory address Compiler

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Advancements in PLL and VCO Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Embedded Systems and FPGA Applications

Physical Sciences → Engineering → Electrical and Electronic Engineering

VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

The design of a register renaming unit

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