Sequential Register Renaming

Abstract

Register renaming unit is a bottleneck in the superscalar cores because it limits the number of instructions and the number of threads that may concurrently be processed. We propose a register renaming unit with linear complexity with respect to the number of instructions simultaneously renamed. The proposed renaming unit renames source operands in a sequential manner following the program order of the instructions. We show that in worst case sequential register renaming may follow contemporary trends with respect to the number of instructions and the number of threads that may be simultaneously renamed.