Register renaming for x86 superscalar design

Abstract

Register renaming eliminates storage conflicts for registers to allow more instruction level parallelism. This idea requires nontrivial implementation, however, especially when registers are accessible with different fields and data lengths. As a result, not all bits in a register are to be updated upon a register write, and a register read may be data-dependent on multiple register writes. We propose two hardware renaming schemes to solve these difficulties: One for its ultimate performance, and the other for its desirable cost/performance ratio. We evaluate these two schemes on an aggressive superscalar machine model for Intel 80/spl times/86 architecture. Simulation results show that the second scheme can effectively reduce the hardware cost while retaining about 99% of the performance of the first.