Reconfigurable Many-Core Processor with Cache Coherence

Xing Han; Jiang Jiang; Yuzhuo Fu; Chang Wang

doi:10.1007/978-3-642-41635-4_21

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Reconfigurable Many-Core Processor with Cache Coherence

Xing Han Jiang Jiang Yuzhuo Fu Chang Wang

Year: 2013 Communications in computer and information science Pages: 198-207 Publisher: Springer Science+Business Media

DOI: 10.1007/978-3-642-41635-4_21

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Keywords:

Computer science Cache coherence Security token Cache Latency (audio) MESI protocol Multi-core processor Protocol (science) Parallel computing Coherence (philosophical gambling strategy) Embedded system Computer architecture CPU cache Cache algorithms Operating system

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Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Reconfigurable Many-Core Processor with Cache Coherence

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