A survey on cache coherence for tiled many-core processor

Abstract

Due to technological parameters and constraints entailed in many-core processor with shared memory systems, it demands new solutions to the cache coherence problem. Directory-based coherence protocols have recently seemed as a possible scalable alternative for CMP designs. Unfortunately, with the number of on-chip cores increasing, many directory design strategies do not scale beyond a dozen cores due to huge energy and area costs for scaling the directories. We explored different NUCA design schemes for tiled many-core architecture, compared several conventional directory protocols, such as full-map directory protocol, sparse directory protocol, duplicate-tag-based directory protocol etc. and analyzed several novel cache protocols designed for many-core processor. At the end, we propose several design directions for scalable and adaptive cache coherence protocols for many-core processor.