Design of FPGA Accelerator Architecture for Convolutional Neural Network

Abstract

With the rapid development of artificial intelligence, convolutional neural networks (CNN) play an increasingly important role in many fields. In this paper, the existing convolutional neural network model is analyzed, and a convolutional neural network accelerator based on field-programmable gate array (FPGA) is designed. In the convolution operation, the parallelization calculation is realized in four dimensions. A parametric architecture design is proposed. Under the three parameters, a single clock cycle can complete 512, 1024, 2048 multiply and accumulate respectively; the on-chip double buffer is designed. The structure reduces the off-chip storage access and realizes effective data multiplexing. The pipeline is used to implement a complete neural network single-layer operation process, which improves the operation efficiency. Compared with CPU, GPU and related FPGA acceleration schemes, the experimental results show that the speed of the design proposed by this paper is 560.2 GOP/s, which is 8.9 times that of the i7-6850K CPU. At the same time, calculated performance and power consumption ratio is 3.0 times that of NVDIA GTX 1080Ti GPU. Compared with related research, the accelerator designed achieves a high performance-to-power ratio in mainstream CNN network computing, and there is no lack of versatility.