Fast RISC-V Firmware Validation with QEMU

Abstract

We present a flexible, system-level/RTL co-simulation approach that utilises existing design artefacts, such as RTL descriptions of peripherals, as well as the device tree of an SoC (e.g. the Rocket Chip Generator), to generate simulation models and configure a QEMU simulation. Such a simulation makes it possible to evaluate hardware/software systems, particularly the effectiveness of the integrated safety mechanism targeted by ISOLDE.