High-Performance ALTEQ Hardware Accelerator

Abstract

With the advent of quantum computing threatening the security of modern public-key cryptography, the standardization of Post-Quantum Cryptography (PQC) is actively underway worldwide. However, optimization research has predominantly focused on software implementations and lattice-based algorithms, leaving a significant gap in hardware acceleration for non-lattice-based schemes, particularly on platforms like FPGAs. This paper addresses this gap by proposing the first hardware/software (HW/SW) co-design to accelerate ALTEQ, a non-lattice-based digital signature algorithm submitted to the NIST PQC Additional Signatures competition. Our approach strategically offloads ALTEQ's most computationally intensive operations, namely hash functions and modular arithmetic, to a dedicated hardware accelerator, thereby it could maximize performance. To the best of our knowledge, this is the first study to investigate hardware acceleration architecture for ALTEQ or similar schemes. The proposed design demonstrates that even algorithms not selected for standardization can achieve significant performance improvements through hardware optimization, suggesting the potential for re-evaluating such schemes for specific application environments and encouraging further research into hardware implementations for a broader range of PQC algorithms.