Power efficient high performance modular hardware accelerator architecture

Abstract

This paper discuss about a power management unit (PMU) which will be implemented in a modular hardware accelerator. The PMU aims to achieve power savings without significantly affecting the performance of the hardware accelerator by timely switching the power state of the device depending on the traffic accessing it and its operating state. The main methods used for power management would be clock and power gating. However some degrees of Dynamic Voltage and Frequency Scaling can be easily added. The PMU will also provide certain level of programmability and will be able to operate accordingly with the software or driver. The functionality of this unit is verified using ABV Verification Test modules.