Implementation of FPGA based 32-bit RISC-V processor

Abstract

This paper introduces the design and FPGA-based implementation of a compact and power-efficient 32-bit processor based on the RISC-V instruction set architecture, tailored for resource-constrained embedded systems. The processor features a simplified 4-stage pipeline that reduces hardware complexity and improves timing performance, making it suitable for low-area applications. A lightweight memory subsystem is integrated, including a 4 KB direct-mapped instruction cache and a 1 KB 2-way set-associative data cache, enhancing access efficiency without large memory demands. Peripheral support for UART, SPI, and PWM is provided via the Wishbone bus, enabling modular system integration. Arithmetic operations are implemented using hardware-friendly unsigned binary multiplication and non-restoring division algorithms to reduce logic utilization. Synthesized and evaluated on a Zybo Z7-20 FPGA, the processor achieves 1.35 CoreMark/MHz and 0.505 DMIPS/MHz, validating its suitability for compact embedded applications. The novelty of this study lies in the design of a compact RISC-V processor core that features a four-stage pipeline, occupies minimal area, and integrates a cache system (a 4 KB direct-mapped instruction cache and a 1 KB 2-way set-associative data cache), offering a balanced microarchitecture that combines low hardware cost with functional completeness. Unlike many previous works, the processor has been validated through real hardware tests with UART, SPI, and PWM modules, rather than relying solely on simulation. In addition, this work provides a detailed comparison against several open-source RISC-V cores such as CV32E40P and Ri5cy, demonstrating comparable or better performance with significantly lower area usage. Its compatibility with OpenRAM and OpenLane flows also makes it advantageous for ASIC implementations. These features collectively position this processor as a practical, low-cost alternative for embedded and edge-computing applications.