Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes

Michele Caon; Clément Choné; Pasquale Davide Schiavone; Alexandre Levisse; Guido Masera; Maurizio Martina; David Atienza

doi:10.1109/tetc.2025.3555869

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Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes

Michele Caon Clément Choné Pasquale Davide Schiavone Alexandre Levisse Guido Masera Maurizio Martina David Atienza

Year: 2025 Journal: IEEE Transactions on Emerging Topics in Computing Vol: 13 (3)Pages: 1003-1018 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/tetc.2025.3555869

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Keywords:

Computer science Scalability Parallel computing Reduced instruction set computing Computer architecture Instruction set Operating system

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Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes

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