Memristive Based In-Memory Computing Using Novel RISC-V Architectures

Abstract

Modern computer architectures currently face a memory bottleneck, causing higher latency and power consumption due to the rapid increase of data in applications. Despite this, widespread adoption makes replacing them challenging. Thus, a crucial need arises for a CMOS-compatible solution with high energy efficiency and substantial parallelism to address the von Neumann bottleneck. Herein, a promising solution is delivered through the concept of in-memory computing enabled by the utilisation of resistive switching devices using the Stanford RRAM Model, constituting a 1T1R crossbar array that meets all of the specified criteria while featuring optimal design density. This paper introduces a novel modification of the widely-adopted RISC-V architecture designed to operate the aforementioned memristive crossbar array using a custom instruction set and specialised hardware blocks, serving as both a comprehensive test bed for the memory system and a compelling proof of concept for the future integration of memristors in computer architectures. This novel design undergoes thorough testing to evaluate its robustness, incorporating an alternating AND operation to simulate the worst-case scenario.