Hardware Acceleration Method Using RISC-V Core with No ISA Extensions

Mateusz Wygrzvwalski; Paweł Skrzypiec; R. Szczygieł

doi:10.23919/mixdes62605.2024.10614026

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Hardware Acceleration Method Using RISC-V Core with No ISA Extensions

Mateusz Wygrzvwalski Paweł Skrzypiec R. Szczygieł

Year: 2024 Pages: 265-269

DOI: 10.23919/mixdes62605.2024.10614026

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Keywords:

Computer science Acceleration Reduced instruction set computing Core (optical fiber) Parallel computing Multi-core processor Instruction set Physics Telecommunications

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Topics

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

Hardware Acceleration Method Using RISC-V Core with No ISA Extensions

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Citation History

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