Implementing RISC-V processor with three-stage pipeline on FPGA

Qiao Zuo; Yujie Li; Wei Liang; Fan Jianning; Ku Hongxu; Xiaodong Zhang; Chong Shen

doi:10.1117/12.3034758

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Implementing RISC-V processor with three-stage pipeline on FPGA

Qiao Zuo Yujie Li Wei Liang Fan Jianning Ku Hongxu Xiaodong Zhang Chong Shen

Year: 2024 Pages: 14-14

DOI: 10.1117/12.3034758

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Keywords:

Reduced instruction set computing Pipeline (software) Field-programmable gate array Computer science Stage (stratigraphy) Embedded system Computer architecture Computer hardware Instruction set Operating system Geology

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Implementing RISC-V processor with three-stage pipeline on FPGA

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