SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology

Dinesh Kushwaha; Ashish Joshi; Abhishek Goel; Rajiv Joshi; Sudeb Dasgupta; Anand Bulusu

doi:10.1109/isqed60706.2024.10528768

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SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology

Dinesh Kushwaha Ashish Joshi Abhishek Goel Rajiv Joshi Sudeb Dasgupta Anand Bulusu

Year: 2024 Pages: 1-8

DOI: 10.1109/isqed60706.2024.10528768

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Keywords:

Static random-access memory Margin (machine learning) Computer science Architecture Computer architecture Memory architecture Mixed-signal integrated circuit Embedded system Electronic engineering Computer hardware Parallel computing Integrated circuit Engineering Operating system

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VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology

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