Power Efficient Approximate Ternary Subtractor for Image Processing Applications

Abstract

The ternary logic has been the most popular in recent years. Many ternary logic-based arithmetic circuits, such as adders and multipliers, exist. Applications such as image processing and video processing application, accurate computation is not necessary, approximate computing is employed to significantly improve circuit parameters such as area, power, and power-delay product. This paper presents a design of an efficient 1-bit approximate half subtractor using the k-map-based methodology, which is used to implement a full subtractor and an 8-bit ternary subtractor. In this work, an error is introduced in the difference signal of the half subtractor. The proposed approximate ternary half subtractor show that power and delay are reduced by 42 % and 55 % in comparison with subtractor using 3: 1 multiplexers and are reduced by 37 % and 38% in contrast with subtractor using 2:1 multiplexer. Finally, the proposed 8-bit subtractor is evaluated using an image processing application.