Power Efficient Approximate Multiplier Architecture for Image Processing Applications

Abstract

The proposed paper introduces a novel multiplier architecture designed specifically for image processing applications. It integrates effective reduction structures into the partial product reduction stage to enhance performance in terms of speed, accuracy, and power consumption, while simultaneously reducing the need for precise computation. Experimental findings reveal that the unsigned multiplier architecture suggested outperforms existing designs in terms of accuracy, reduces power consumption by up to 50.84% compared to previous designs, and improves power-delay product by up to 59.52%. The effectiveness of the suggested architecture has been validated using image processing applications.