Roadmap for ferroelectric domain wall memory

Abstract

Commercial nonvolatile Ferroelectric Random Access Memory employs a destructive readout scheme based on charge sensing, which limits its cell scalability in sizes above 100 nm. Ferroelectric domain walls are two-dimensional topological interfaces with thicknesses approaching the unit cell level between two antiparallel domains and exhibit electrical conductivity, distinguishing them from insulating matrices that are uniformly ordered. Recently, novel research has been devoted to utilizing this extraordinary interface for the application in nonvolatile memory with nanometer-sized scalability and low energy consumption. Here, we pay more attention to the development of the domain wall memory technologies in the future with challenges and opportunities to design planar and vertical arrays of the memory cells in the CMOS platform.