FPGA architecture for convolutional neural network training

Abstract

Convolutional neural networks (CNNs) have been gradually applied to aerospace equipment in recent years. However, CNN requires a significant amount of hardware resources, while parameters need to be updated for different tasks in space. We propose an FPGA architecture for CNN training through a multi-module collaborative design strategy. On the basis of the intra-layer parallelism, we analyze the data storage and the operations to deduce forward and backward propagation on embedded devices. Based on the experimental results, the working frequency can reach 250 MHz and the performance is 15.9 GOPS. The resource usage and efficiency of this design are superior to those of other similar hardware acceleration platforms.