Hysteresis-Free Solution-Processed 2-D MoS₂ Flake-Thin-Film Transistors With Improved Operational Stability

Abstract

An interface trap negatively affects the performance of a thin-film transistor (TFT). In the current study, we demonstrate hysteresis-free solution-processed MoS2 TFTs with a significantly reduced trap density of $3.7\times 10^{{10}}$ cm $^{-{2}}$ using a poly(methylmethacrylate) (PMMA) dielectric in a top-gate top-contact (TGTC) device structure, which is much lower than that with a SiO2 back-gate dielectric layer ( $7.9\times {10}^{{11}}$ cm $^{-{2}}$ ). The TFTs show a field-effect mobility of 7 cm2/V s for both forward and reverse scans, with an ON/ OFF current ratio of $10^{{6}}$ . In addition, after 3000 s of the bias-stress test, the drain current of the device degrades by only 7%.