Fault-tolerant selt-timed circuits

A. A. Zatsarinny; Yu. A. Stepchenkov; Yuri Diachenko; Yu. V. Rogdestvenski; L. P. Plekhanov

doi:10.17073/1609-3577-2022-4-298-304

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Fault-tolerant selt-timed circuits

A. A. Zatsarinny Yu. A. Stepchenkov Yuri Diachenko Yu. V. Rogdestvenski L. P. Plekhanov

Year: 2023 Journal: Izvestiya Vysshikh Uchebnykh Zavedenii Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering Vol: 25 (4)Pages: 298-304

DOI: 10.17073/1609-3577-2022-4-298-304

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Abstract

The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to faults. Redundant ST coding and two-phase discipline ensures that ST circuits are more soft error tolerant than synchronous counterparts. Duplicating ST channels instead of tripling reduces the fault-tolerant ST circuits’ redundancy and retains their reliability level compared to synchronous counterparts.

Keywords:

Fault tolerance Electronic circuit Computer science Redundancy (engineering) Coding (social sciences) Error detection and correction Reliability engineering Distributed computing Algorithm Electrical engineering Engineering Mathematics

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Fault-tolerant selt-timed circuits

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